PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

Create constraints (XDC file)

Hi

I want to you use the Pynq-Z1 base overlay to generate bitstream (.bit file) for my ZC706 board.How can I create the constraints (.xdc file) for this board? (is the one in the/boards/Pynq-Z1/base/vivado/constraints/ helpful?)

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Use the xdc for the ZC706.
You will need to reroute the Pynq-Z1 base overlay block diagram I\O ports to the ZC706 I\O ports, obviously.
You can change the names or do it in the wrapper.
Best regards

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Thank you for you reply

Unfortunately, I didn’t understand the first line " Use the xdc for the ZC70"! is there any out-of-the-box xdc file I can use?

As I’m a beginner I don’t know how to reroute the Pynq-Z1 base overlay I/O ports to the ZC706 I/O ports. Any help would be appreciated.

You need to assign ports in your design to FPGA pins.
You are using a different board, and a chip with a different pin configuration, so you can’t use the existing XDC for the Z1/Z2 boards.

A constraint will have the port name from your design, and the FPGA pin name.

You can typically find the pin names for a board in a reference XDC file, or in the user manual for the board.

You can use an existing XDC file for the ZC706 and delete parts you don’t need, and rename the port names to match what you have in your design, or you can create a new XDC file (definitely not recommended for a beginner).
You can also assign pins in Vivado using the GUI which is probably the best place for you to start. After synthesis, you can open the synthesized design, and go to the IO planning view. You can see a quick example assigning pins in the Vivado IO planning
here (around 7 minutes):

See docs here:

If you have further questions, you would be better posting on the Xilinx support forum as IO planning isn’t PYNQ specific. https://forums.xilinx.com

Cathal

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Thank you Cathal for your answer… I’ll try it out