Exported design from vivado does not contain all ips

i have created a block design following tutorial Tutorial: AXI Master interfaces with HLS IP
I have generated a Vitis code in Cpp, as here:

I have created the design and exported the bitstream file. See the picture attached of my design:

However, when I load the bitstream file in the pynq jupyter file, I find the following IPs listed in the ip_dict.:

I have reviewed the design, remade it, and I cannot find where the error is? Does anyone know why this is happening? What should I do?

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Hi @GGChe,

Have you checked that the memory offset of your IP is valid?

Which board are you using? Which version of Vivado? Which version of PYNQ?


I had to reset the kernel and re-run the jupyter and it seems to be running well. Solved by now. Thanks!

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