i have created a block design following tutorial Tutorial: AXI Master interfaces with HLS IP
I have generated a Vitis code in Cpp, as here:
I have created the design and exported the bitstream file. See the picture attached of my design:
However, when I load the bitstream file in the pynq jupyter file, I find the following IPs listed in the ip_dict.:
I have reviewed the design, remade it, and I cannot find where the error is? Does anyone know why this is happening? What should I do?