Failing Timing with Dual DMA

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1

Hello,

I’m having some issues with meeting timing when synthesizing my design.
The goal: Process two 32-bit vectors in parallel and write the results to DDR.
Design background:

  1. Each IP, two total, contains a CDMA and DMA reading/writing 32-bit data.

  2. PL clock set at 250 Mhz, CPU at 450 Mhz, DDR at 250 Mhz.

  3. The interconnects have the crossbar-size set to 64-bit width.

  4. HP’s are set to 64 bit width.

Previously, I working with a single IP at 32-bits, timing was met at the above mentioned speeds. I’m attempting to process more data by running two IPs each on upper and lower sections of the original data - Split in PS. My hope is to double or greatly improve throughput.

Based on this design, are there any flaws, fundamental issues I’m overlooking?

Thanks

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2

Dear @Darknessoup,

Welcome to the PYNQ community.

Unfortunately, this topic is outside of the scope of the PYNQ forums. You may be better off asking this question in the Adaptive computing forums. AMD Customer Community

Mario

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