Hello,
The board is ZCU104. When I use DMA to transfer data from memory to GPIO output. The clock is set to 375MHz, it could work. But when set to 500MHz, the system throws out an error: the DMA channel not idle. So I want to know the DMA support Max speed is (MM2S)? If I want to use 800MHz DMA speed, How to achieve it? Thank you!
Best regards,
Which clock are you referring to when you say it is set to 375MHz?
Do you just update the clock to 500MHz from PYNQ? If you do this without updating your overlay (the Vivado deisgn) then your design is probably not meeting timing at 500MHz and causing errors.
The max speed will depend on your whole design and what Vivado can achieve. Have you experience with FPGA design? Trying to meet a particular clock speed is referred to as timing closure. You may want to read up on this.
Cathal
Hi, cathalmccabe,
I use the PL clock. And the max frequency could be set to 1600MHz.
Normally, I will set clock by PYNQ.
As I think, the PL clock value could be modified by PYNQ program, so It doesn’t matter how much is the clock value set in Vivado, right?
Maybe, the problem come from this(below figure). Do you know how to solve it? Thank you!
Best regards,
No, the maximum value of your design is determined by the Vivado implementation of your design, not the max value you can set from PYNQ. You can only set the clock in PYNQ to the max value as determined from Vivado.
Cathal
Thank you!
By the way, the problem maybe comes from the below warning, do you know how to solve it? Or I need ask this question in Xilinx Forum. Thank you!
This is reporting the max clock for this part of your design. You can’t clock this port at more than this.
Cathal
