Paralle data transfer to multiple DMAs

Hi,

Is it possible to transfer multiple data to multiple AXI DMA’s at the same time.
I tried the below code , but i was not able to increase the performance of my design

image

(I am not sure if the above code starts all the DMAs at a time)
(I connected all DMA’s to different slave and master ports)

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@tn007

For a direct memory access aka DMA.
You need to understand it is referring to a section of memory fetching.
This is sequentially access either WR/RD.
So if there is only one and only one physical memory interface aka DDR3.
The interleaving style accessing does not really increase performance.
Unless two physical interface are allowed and two DMA engine is holding each individually.
This part also require more understanding on mutex switch and memory crossing.

However, if you are considering PL BRAM and slicing it then accessing via ZYNQ ARM processor this is another store as the bottle neck now changed to the AXI throughput.

As for code itself you can do to mimic.

Enjoy~

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Thank you

@tn007

A fun sharing about DDR.
latest DDR5 is interesting about splitting the old DDR4 data bus from 64 back to 2x32bits.
And extending the bank twice, so we can see speed doesn’t mean anything when zero padding is the killing point.

Enjoy~

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