I have one high-speed FPGA board(ZCU104), with a clock 500MHz, output through GPIO, connect with RF cable. So different I/O has a different time delay. I could do timing constraints when synthesizing using Vivado to compensate for the time difference. But as you know, it is not convenient(one time, only set one-time delay parameter, then wait a long time to generate bit file), what I need is to tune the time delay in PYNQ software. Does anyone know if there is one IP I could use? Or I could set it in PYNQ system? Thank you in advance.

Best regards,

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Can you explain in more detail what you are trying to do?
What IO standard are you trying to use?
This doesn’t seem like a PYNQ question. PYNQ provides Python APIs to control your PL design. If you can do something in a standard Zynq (C/C++) flow to control your IP, then you can also do this with PYNQ.


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