Dear PYNQ community,
using Vivado, I have created a design to be used as a timing controller in a physical experiment. We need to use an external reference clock of 54.1667 MHz, which comes from an external system and I succesfully managed to get this via some IO pin into the FPGA. Since this external system is not always at hand, I introduced a “simulation mode” where an internal clock (FCLK0) is set to 54.1667 MHz (dividers 6 and 4 from the ARMPLL @ 1.3 GHz). This is quite a fortunate coincidence.
From Vivado, everything works.
Now, using the Jupyter framework, the bitfile can be loaded and everything works – in principle. The simulated clock, however, is set to 41.667 MHz. It seems that it is derived from the IOPLL @ 1.0 GHz. Indeed, I found this forum post:
> At present the PYNQ framework will only consider the IOPLL when setting a clock frequency
With the IOPLL, I can only generate 50 MHz and 55.5556 MHz; the magical 54.1667 MHz is not possible.
But @PeterOgden also says:
> Supporting other PLL settings is something we can look into in the future.
Can we expect to access the PLL settings from Jupyter in near future?
Could you propose another method of changing these settings from outside Vivado / without JTAG access?