PYNQ-Z1: FCLK0 tied to ARM PLL?

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Dear PYNQ community,

using Vivado, I have created a design to be used as a timing controller in a physical experiment. We need to use an external reference clock of 54.1667 MHz, which comes from an external system and I succesfully managed to get this via some IO pin into the FPGA. Since this external system is not always at hand, I introduced a “simulation mode” where an internal clock (FCLK0) is set to 54.1667 MHz (dividers 6 and 4 from the ARMPLL @ 1.3 GHz). This is quite a fortunate coincidence.

From Vivado, everything works.

Now, using the Jupyter framework, the bitfile can be loaded and everything works – in principle. The simulated clock, however, is set to 41.667 MHz. It seems that it is derived from the IOPLL @ 1.0 GHz. Indeed, I found this forum post:
https://discuss.pynq.io/t/pl-fclk0-changes-as-soon-as-overlay-loads-bitfile/818/6
> At present the PYNQ framework will only consider the IOPLL when setting a clock frequency

With the IOPLL, I can only generate 50 MHz and 55.5556 MHz; the magical 54.1667 MHz is not possible.

But @PeterOgden also says:
> Supporting other PLL settings is something we can look into in the future.

Can we expect to access the PLL settings from Jupyter in near future?
Could you propose another method of changing these settings from outside Vivado / without JTAG access?

Thanks, Markus

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If you want a specific clock,add a clock wizard to your PL design, and synthesize the clock you need inside the device.

Which board are you using, and which pins do you plan to use to get your external clock into your board? Be aware, you may not be able to provide a clock through any pin and expect to get a clean 50MHz+ clock input to the device.

Cathal

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Thanks @cathalmccabe for your fast reply.

I will try the clock wizard later, but it sounds as a nice solution.

The board is a pynq-z1; as external CLK input I am using the pin “41” on the PCB; according to the pynq-z1_sch.pdf this is called “IO_L14P_T2_SRCC_13” (hence, can be used as a clock), and wired as Y9.
According to oscilloscope traces, I am getting a clean and nice clock signal. For debugging, I am routing the Y9 to some other pin, let-me-see, io26 on PCB and U5 on the chip.

4

Clock wizard for the win!

Long anser: instead of using the ARM PLL (26x50, then divided by 6x4=24 to 54.1667) the wizard takes a 250 MHz clock (that I am using somewhere else in the design); the wizard divides by 5 and then uses a PLL to go up to 1.3 GHz and then down again to the desired magical frequency.

Thanks to @cathalmccabe again.