Hello,
I am working on a zynq based project on pynq z2, where I have a AXI stream IP (say, an adder - single master, single slave) with fifo’s on either ends.
The goal is to run the IP block at variable frequency by muxing the clocks generated from PLL.
Question:
How to send the data for the select lines of the mux from pynq, so that I can control the frequency of the IP from pynq as the data keeps streaming in at PS frequency. Any idea in this regard would be great.
Block Design:
Pynq Image Version: v2.7
Board: Pynq z2
Vivado version: 2020.2
Thanks in advance.