Hi, I’m trying to get multiple outputs from the RGB-to-YUV4 acceleration kernels. I made a design like this: [Screenshot from 2022-04-28 12-53-59] Is that the right way to handle multiple streams using AXI4-Stream Switch? On IPython, since the DMA only has sendchannel.transfer() and recvch…

Hi @haipnh , This is not a PYNQ-related question. You may be better off asking in the Xilinx forums You will need one DMA per each stream. Mario

Handle multiple streams with AXI4-Stream Switch

haipnh April 28, 2022, 8:18am 3

Sure. I tested another solution that uses xf::cv::merge() to merge the internal outputs, then convert it to data stream.

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