Handle multiple streams with AXI4-Stream Switch

[haipnh]

Hi,

I’m trying to get multiple outputs from the RGB-to-YUV4 acceleration kernels.

I made a design like this:

1. Is that the right way to handle multiple streams using AXI4-Stream Switch?

2. On IPython, since the DMA only has sendchannel.transfer() and recvchannel.transfer(), how to make it handle multiple streams?

[marioruiz]

Hi @haipnh,

1. This is not a PYNQ-related question. You may be better off asking in the Xilinx forums
2. You will need one DMA per each stream.

Mario

[haipnh]

Sure. I tested another solution that uses xf::cv::merge() to merge the internal outputs, then convert it to data stream.