I working on RFSoC4x2 ZU48DR (v2.6 Gen3). I implemented the base design [1] and executed it using the notebook available in [2]. I am trying to do a loopback. The code in the notebook runs fine. Now I want to bypass the mixer in the RF-ADC side from the notebook itself. So that I can visualize the signal i generated from RF-DAC directly. I don’t want to change the base design in vivado as that would require me to do changes in python files for PYNQ. The current design receives the signal at RF-ADC, Mixes it with signal generated form NCO and outputs I and Q (mentioned as Real and Imaginary in the block diagram). If i bypass mixer using python what would be the output from one of these output be as the other would give me the input signal (the rfdc ip has 2 output real and imag or I and Q).
[1] RFSoC-PYNQ/boards/RFSoC4x2/base at master · Xilinx/RFSoC-PYNQ · GitHub
[2] RFSoC-PYNQ/boards/RFSoC4x2/base/notebooks/rfdc/01_rf_dataconverter_introduction.ipynb at master · Xilinx/RFSoC-PYNQ · GitHub