PYNQ: PYTHON PRODUCTIVITY

How to debug when I got stuck at "DMA wait()"

I use AXI streaming in the Sobel filter implementation, but I got stuck at the dma.recvchannel.wait(). And I need some suggestions to help me debug. My board is PYNQ-Z2, and input data is grayscale image in 1080x1920

My C++ code in HLS:

void video_2dfilter(wide_stream* input_stream, wide_stream* output_stream) {
#pragma HLS INTERFACE axis depth=20000 port=input_stream bundle=INPUT_STREAM
#pragma HLS INTERFACE axis port=output_stream bundle=OUTPUT_STREAM

#pragma HLS INTERFACE s_axilite port=return bundle=CONTROL_BUS

	uint8_t window[3][3];
	uint8_t line_buffer[2][MAX_WIDTH];
#pragma HLS ARRAY_PARTITION variable=line_buffer complete dim=1

	int8_t filter_horizontal[3][3] = {{-1,-2,-1},{0,0,0},{1,2,1}};
	int8_t filter_vertical[3][3] = {{-1,0,1},{-2,0,2},{-1,0,1}};

	row_loop: for (int row = 0; row < MAX_HEIGHT; row++) {
		col_loop: for (int col = 0; col < MAX_WIDTH; col++) {

#pragma HLS pipeline
			for (int i = 0; i < 3 ; i++){
				window[i][0] = window[i][1];
				window[i][1] = window[i][2];
			}

			window[0][2] = (line_buffer[0][col]);
			window[1][2] = (line_buffer[0][col] = line_buffer[1][col]);
			window[2][2] = (line_buffer[1][col] = input_stream->data);
			++input_stream;

			// handle boundary
			if (row == 0 || col == 0 || row == (MAX_WIDTH - 1) || col == (MAX_WIDTH - 1)) {
				output_stream->data = 0;
			} else{
				output_stream->data = ABS(filter(window, filter_horizontal)) + ABS(filter(window, filter_vertical));
			}

			// streaming attr setup
			output_stream->user = (row == 0 && col == 0)? 1: 0;
			output_stream->last = (row == MAX_HEIGHT-1 && col == MAX_WIDTH-1)? 1: 0;
			++output_stream;
		}
	}
}

My Block Design and DMA configurations, where I add AXI Stream Interconnection to control dataflow route to various convolution kernels I will include in the future.


My Python code on Jupyternotebook:

What size is your input_buffer?

Buffer length register is 2^14. This is the max amount of data you can transfer in one transaction. You probably want to make this bigger.

Why are you using the AXI stream interconnects? You could connect directly to the DMA.

Cathal