Implementing DDS on PYNQ-Z1

Support
1

Hi all,

I’m using PYNQ Z1 (Release 2019_10_03 3f63450) and I’m trying to implement a DDS by modifying the tutorial for implementing a FIR filter with PYNQ Z1. I replaced the FIR IP with the DDS IP. But when I ran the code bellow, it enters some sort of infinite loop. I looks like it is stuck waiting for a response.

from pynq import Xlnk
import numpy as np
from pynq import Overlay
import pynq.lib.dma

Load the overlay

overlay = Overlay(‘/home/xilinx/pynq/overlays/wave/wave.bit’)

Load the FIR DMA

dma = overlay.wave.dds_dma

Allocate buffers for the input and output signals

xlnk = Xlnk()
in_buffer = xlnk.cma_array(shape=(n,), dtype=np.int32)
out_buffer = xlnk.cma_array(shape=(n,), dtype=np.int32)

samples = np.ones(n)

Convert samples to 32-bit integers

samples = samples.astype(np.int32)

Copy the samples to the in_buffer

np.copyto(in_buffer,samples)

Trigger the DMA transfer and wait for the result

dma.sendchannel.transfer(in_buffer)
dma.recvchannel.transfer(out_buffer)
dma.sendchannel.wait()
dma.recvchannel.wait()

Free the buffers

in_buffer.close()
out_buffer.close()

Could you advice on how to debug this problem?

Thank you!

bitstream_tcl.zip (168.4 KB)

2

Can you attach a block design instead of the tcl file? We can have a quick look.

3

Hi @rock,

Thank you for your response. Here are the files of my project: https://www.dropbox.com/s/tkvralod8bsvdno/dds6.zip?dl=0. And here is a picture of my block design:

block_design
block_design1807×401 49.4 KB

4

Have you verified the IP works? Where did you get the DDS IP? Also, we need more information about the error message / where system hangs / etc.