Inquiry on 8×1 Vector Data Transmission in Simulink and RFDC IP AXI4-Stream Sample & Clock Configuration

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Hello I’m using RFSoC 4x2 board, and trying to make an OFDM code based on Simulink HDL coder. I have a question regarding the generation of an OFDM signal using Simulink HDL Coder. I have set the sampling rate in Simulink to 60 MHz, with each signal being 32 bits wide. In order to achieve an OFDM signal bandwidth of at least 400 MHz, I am processing 8 channels in parallel.

Therefore, I configured the data in Simulink as an [8×1] vector. At the final stage, when sending the data out via an AXI4-Stream, I set the Interface Setting “Sample Packing Dimension” to “All” so that in one clock cycle, all 8 vector elements are transmitted simultaneously.

As a result, the OFDM IP is configured such that the AXI4_stream_master_tdata becomes 32 bit × 8 = 256 bit.

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In this configuration, each element has a sampling rate of 60 MHz, and with 8 elements processed in parallel, the effective sampling rate becomes 480 MHz.

Subsequently, in Vivado’s RFDC IP, I plan to apply an x8 interpolation, which would yield an RF-DAC sampling rate of 480 Msps × 8 = 3.82 GSPS. However, given that the data sent in one clock cycle is grouped into 8 elements, I have a few questions:

  1. Samples per AXI4-Stream Setting:
    Should I set the “Samples per AXI4-Stream” parameter to 8 so that the RFDC IP processes the data in 8 parallel units, matching the [8×1] vector arrangement from Simulink?

  2. Clock Frequency and Target Frequency Settings:
    When using x8 Interpolation/Decimation with “Samples per AXI4-Stream” set to 8, the required AXI4-Stream clock becomes 60 MHz. Does this mean that I should set the sampling rate in Simulink to 60 MHz and also configure the HDL Coder’s target frequency to 60 MHz? I am under the impression that the clock frequency should be higher than the sampling rate, so I wonder if having these frequencies equal might pose a problem.

  3. Consistency Between HDL Coder and RFDC IP:
    In summary, when generating an OFDM IP with Simulink HDL Coder that sends 8-element vectors via the AXI4-Stream, must the RFDC IP also be configured with “Samples per AXI4-Stream” set to 8 in order to process the data in the same 8-parallel manner? Additionally, should the target frequency specified in HDL Coder be identical to the required AXI4-Stream clock in the Vivado RFDC IP? And if the target frequency must always be higher than the sampling rate, might it be necessary to incorporate an additional FIR Compiler IP?

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Hi @Jina ,

  1. I don’t have experience with Simulink, but I believe that is correct as it will use 16x2x8=256 bits as data. My design works with real data, so, I am not sure with your case.
  2. Clock shown in the target frequency is for the AXI stream ports of PL design. It is not about sampling rate. RFDC separates ADC/DAC into channels to achieve the high bandwidth. Check out PG269 for further information. FYI, RFSoC 4x2 uses Gen3 RFDC.
  3. Interpolation and decimation of RFDC has its own filter (see PG269). I am trying to do OFDM as well, however, in my design, I each channel uses different sub-carrier. Thus, this makes interpolation/decimation filters to be counteractive for my design. So, interpolation/decimation doesn’t work for me. If you aren’t trying something similar, you should be fine. You should always test your design with ILA or something.

Hope this helps!