Dear all
I am using PYNQ 3.0.1 with RFSoC 4x2.
I have a question about controlling AXI4 stream of RFDC with decimation/interpolation > 2.
By default (case0 in the below figure), it is similar to the base Overlay
- I/Q for both ADC and DAC
- Interpolation and decimation = 2
- Samples per cycle = 8 for ADC and 16 for DAC, so AXI stream is (16 bits) x (8 samples) x 2
- clk_adc and clk_dac output are both 160 MHz, and they are directly used to control the AXI4 streams.
- tvalid is always 1 for each clock-cycle
This default case is working fine. All the 8 x 2 samples in the AXI4 stream are running.
Next, I tried two more cases:
As you can see in these two cases, the only difference is in decimation / interpolation.
- case1: decimation / interpolation = 4, so clk_adc and clk_dac become 80 MHz. Still keeps tvalid as 1 in each clock-cycle
- case2: decimation / interpolation = 8, so clk_adc and clk_dac become 40 MHz. Still keeps tvalid as 1 in each clock-cycle
My understanding is that, if decimation / interpolation is doubled, the clock for AXI4 stream (clk_adc / clk_dac) should be half, then we still transmit and receiver all the (16 bits) x (8 samples) x 2 streaming data in each clock-cycle by keeping tvalid as 1 always.
However, the problem occurred:
- case 1: Only 4 of the 8 samples (64 bits) at LSB will be running at receiver.
- case 2: Only 2 of the 8 samples (32 bits) at LSB will be running at receiver.
The rest of the data samples are either 0 or small value.
In there anything wrong in my understanding?
While decimation / interpolation > 2, what should one do to control the AXI4 stream correctly?
Thank you in advance.