Creating custom overlays on RFSoC 4x2


I am currently trying to implement some custom IP into the base RFSoC overlay so I can start to creating my own application. I am new to PYNQ, and I am struggling to get PYNQ to recognize my IP blocks in the overlay and I am trying to figure out what I am missing. Currently, I am just trying to get any IP block to be recognized and communicate with its registers.

When I try to check if an IP block is recognized, I use the “?” operator, i.e

from pynq import Overlay
ol = Overlay('base_custom.bit')

Then I check to see if the changes I made are reflected under “IP Blocks”

Here is what I have tried…

I created a custom IP block, which for now is just the default AXI Lite block that you can create with Vivado, I plan on eventually turning it into an adder to test writing inputs and reading outputs off of it. It is connected to the master of an AXI interconnect IP block(axi_hpm0_lpd) and connected to the slave of another axi interconnect IP block(axi_interconnect_1), which is then connected to one of the slave PL-PS ports of the Zynq PS. This does not seem to reflect any change in printed overlay(“ol?”). I also have tried connecting the Master port directly to the slave of the PS system, but still no dice.

I added a AXI GPIO block, and called it “axi_gpio_dummy”. At first, I left the GPIO output unconnected. When I did that, the block did not appear in the overlay.

As a way to see if I could get anything to reflect a change in the overlay, I changed the name of leds_gpio to leds_gpio_fubar. That did reflect in the overlay(“ol?”)

Something I noticed in the generated .hwh that I thought could hint towards the problem was at the very bottom of the file, under MEMORYMAP and PERIPHERALS, the IP blocks I was adding was not reflected there. They were being described throughout the rest of the hwh file, just not there, and it seems that is probably the place where PYNQ parses to figure out how to write to certain IP blocks.

I have attached the bit file and the hwh file below. They are a google drive link because they are too big.




If I understand correctly, you have modified the base Overlay but you did not see the modifications applied via ol?, is it true?

After having modified the Overlay, did you generate a new bitstream and implemented it on your RFSoC 4x2? What did you do for that step? Did you do like in this tutorial?
(Tutorial: Creating a hardware design for PYNQ)

I followed the instructions very similar to the link you just posted. The steps I followed are practically identical to the steps for applying AXI GPIO. I do not however generate a tcl script, but that does not seem to be necessary for PYNQ(correct me if I am wrong).

I am going to follow that exact tutorial(or at least to the greatest extent on the base image of the RFSoC 4x2) shortly and see if it yields different results.

Edit: I am using Pynq 3.0 and I compiled the base image in Vivado 2022.1

Hi @joe,

Welcome to the PYNQ forum.

Looks like you have not assigned an address to the GPIO.
In your block design, go to Address Editor and click Assign All image

Then rebuild the bitstream.

In this view, make sure no segment is unassigned.


That seemed to do the trick. Thanks!

1 Like

This topic was automatically closed 3 days after the last reply. New replies are no longer allowed.