I am trying to follow the “Vivado Design Suite Tutorial: Programming and Debugging (UG936)”. In this tutorial, FPGA board AMD Kintex KC705 is used. The IP source files like “sine_high.xci” file are locked (scroll down to “Using the Netlist Insertion Method to Debug a Design”) on Vivado 2024.1. Is there anyway where I can configure the file to match my board?
Hi @katrina.rg,
Welcome to the PYNQ community.
You may be better off asking this question in the Xilinx forum.
Mario