Yes, you can have one HP port enabled on the Zynq PS, and connect all your AXI masters via an AXI Interconnect block to the same HP interface.
You may also be interested in this tutorial:
https://discuss.pynq.io/t/tutorial-axi-master-interfaces-with-hls-ip/4032
You can remove the DMA and allow the HLS IP to access memory directly. Essentially the DMA functionality is absorbed into the HLS IP.
If the DMA is hanging/not completing, it is probably due to the HLS IP not generating the expected amount of data/TLAST issue as mentioned by other poster.
You shouldn’t really be setting ap_start with a constant. You would be better adding the control signals to the AXI lite interface.
We can’t help with warnings if you don’t show them in your post. Even though you say the design builds, there could be an issue with one of the warnings that you shodul address.
Cathal