PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

Looking for the higher level HDL files

I’m fairly experienced with the standard FPGA and Embedded design flows for Vivado. I was hoping to find the source files for the design, at a precompiled level on the GIT site, but alas, I’m finding lots of the software stuff, but only .bit files for the hardware items. Specifically, I’d like to see the device view in Vivado of an overlay design, with the LogicTools instantiated. Any guidance is appreciated. I didn’t see LogicTools in the IP library. I suspect they are part of the Logic Analyzer, but haven’t confirmed.

Thanks,

JJ

See docs here for rebuilding logictools. You should be able to see how the design is built, and all custom IP is in the “ip” folder in the PYNQ GitHub repo. : https://pynq.readthedocs.io/en/v2.4/pynq_overlays/pynqz2/pynqz2_logictools_overlay.html#rebuilding-the-overlay

Cathal