Makefile Failure - Pynq 2.7, Ubuntu 20.04, Vivado 2020.2

Hey all, apologies for this post if it doesn’t meet rules, I’m new to the PYNQ world but have had difficulty trying to compile the base Pynq-Z1 overlays in my environment. I’ve run the makefile (using the command make all) and directly from Vivado 2020.2 using the TCL scripts (source ./build_ip.tcl). I made sure to check the Releases page for PYNQ 2.7 to make sure I had the correct version of Vivado, and made sure that Ubuntu 20.04 was listed as supported. What am I doing incorrectly, or what do I not have configured correctly?

My error message output (following a successful compile of color_convert I believe) is the following:

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
bad lexical cast: source type value could not be interpreted as target
    while executing
"rdi::set_property core_revision 2204062314 {component component_1}"
    invoked from within
"set_property core_revision $Revision $core"
    (file "run_ippack.tcl" line 937)
INFO: [Common 17-206] Exiting Vivado at Wed Apr  6 23:14:43 2022...
ERROR: [IMPL 213-28] Failed to generate IP.
INFO: [HLS 200-111] Finished Command export_design CPU user time: 11.72 seconds. CPU system time: 0.75 seconds. Elapsed time: 13.75 seconds; current allocated memory: 239.345 MB.
command 'ap_source' returned error code
    while executing
"source color_convert/script.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $arg] "

INFO: [HLS 200-112] Total CPU user time: 24.19 seconds. Total CPU system time: 1.83 seconds. Total elapsed time: 26.04 seconds; peak allocated memory: 235.505 MB.
INFO: [Common 17-206] Exiting vitis_hls at Wed Apr  6 23:14:46 2022...
child process exited abnormally
INFO: [Common 17-206] Exiting Vivado at Wed Apr  6 23:14:46 2022...
make: *** [makefile:10: hls_ip] Error 1

Any help would be greatly appreciated.

I corrected the issue: After doing a bit more digging, I found that this was a bug in Vivado that was patched by Xilinx. Apologies for the obvious question, but for anyone else who could be dealing with the same issue, see here:

https://support.xilinx.com/s/article/76960?language=en_US

2 Likes

Thanks for posting back with your solution.

Cathal

1 Like