So first I should clarify I mislabled my expectations, I think it should be:
Memory_resmap_V: 0xA0020000 + 0x1000 (bin_to_res_0)
align_V: 0xA0020000 + 0x2000 (bin_to_res_0)
Memory_toneinc_V: 0xA0034000 + 0x1000 (resonator_dds_0)
Memory_phase0_V: 0xA0034000 + 0x2000 (resonator_dds_0)
So Pynq isn’t flipping addresses as my post implied, just skipping one offset and not discovering both cores fully.
@rock Yes, I think you are correct. This block has two AXI lite HLS slaves and I’d expect them to both be accessible. If they got mapped to one base address at 0xA002 0000 then I’d have guessed I could just use a larger offset for the higher regs. I tried (0xA0020000-0xA0034000) + 0x1000 to get at where I thought resmap should be but “ValueError: Offset cannot be negative.”
As for accessing:
print(ol.gen3_reschan_0.S_AXI_CTRL.read(0x1000)) → 0
print(ol.gen3_reschan_0.S_AXI_CTRL.read(0x2000)) → 0
print(ol.gen3_reschan_0.S_AXI_CTRL.register_map) → RegisterMap { align_V = Register(align_V=0, RESERVED=0) }
This last one I’m surprised about as that register should be located at
0xA0020000 + 0x2000. I’m not sure if any of these results are correct and I’m not yet able to get the system online (in part because I need to load the resmap!).
As for why I’m trying to do things this way, see my second comment in this thread over on the xilinx forums. Perhaps there is a better way.