Type: Overlay
String form: <pynq.overlay.Overlay object at 0xb4350e50>
File: /usr/local/lib/python3.6/dist-packages/pynq/overlay.py
Docstring:
Default documentation for overlay /home/xilinx/pynq/overlays/suma/axi4stream_1.bit. The following
attributes are available on this overlay:
IP Blocks
axi_dma_0 : pynq.lib.dma.DMA
Hierarchies
None
Interrupts
None
GPIO Outputs
None
Class docstring:
This class keeps track of a single bitstream’s state and contents.
Would you know what the cause may be? Thanks in advance!!
Hello,
This is expected. Your IP only has AXI stream ports, and no AXI control interface. This means you can’t interact directly with your block, you can only control the DMA to read or write to the AXI streams.
Depending on what your design does, this may be OK. E.g. you simply stream data to your IP, and read back a stream of results.
If you added and AXI (lite) control interface to your IP, you would see it from Python, but as I said, you may not need to do this.
Hi @cathalmccabe can we do processing data with simply stream data to your IP, and read back a stream of results without calling IP in jupyter notebook?
I meant, do DMA automatically passing data to and from IP without calling from python?
is there any working example for this?
You could build an IP with an AXI master. The IP can then access memory directly without a DMA/control from PS.
Doing this in HLS is reasonably straightforward.
You would still need to allocate a memory buffer in the PS for the IP to use and pass the address to the IP. Once you do this initial setup the IP can work autonomously.
You can google for the HLS user guide/Xilinx forums for examples of how to do this.
Thank you for your explanation and answer @cathalmccabe. I really appreciate it.
However, I didn’t find any example on AXI stream data FIFO example to processing stream data. Would you mind let me know the link/examples?
By default, the IP will access address 0x0 (this is what the example uses).
“offset” in the prgama above adds a register for the base address of the memory buffer the IP should use.
You should also add an AXI lite for the control interface, otherwise this gets generated as wires by default.
#pragma HLS INTERFACE s_axilite port=return
I think the address register is usually (always?) at 0x10, but you can check this in the hardware header file (*_hw.h) for the example driver that gets generated for the IP).
You should see something like this:
// control
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
...
// 0x10 : Data signal of a
// bit 31~0 - a[31:0] (Read/Write)
In PYNQ, the host OS manages memory, so you can’t just let the IP use 0x0. This is why “offset” was needed.
You would allocate a memory buffer in PYNQ, get and write the physical address to the IP (using the offset register).
Then start the IP - write ap_start in the control register. You can optionally set auto_restart.
Then wait for the result check ap_done in the control register.
