MMIO AXI Lite access through an interconnect in IP Subsystem

rock · April 28, 2020, 6:55pm

I think you can try
ol.gen3_reschan_0.register_map

as shown in

Xilinx/PYNQ/blob/master/boards/ZCU104/base/notebooks/board/register_map_intro.ipynb

{
 "cells": [
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "# Introduction to the Register Map\n",
    "\n",
    "It is possible to access the register map for IP in the overlay directly. This functionality requires that the `.hwh` file is distributed along with the bitstream. This can be generated from Vivado.\n",
    "\n",
    "In this example we are going us the GPIO blocks controlling the buttons and LEDs to demonstrate how to explore and interact with the register map.\n",
    "\n",
    "First we need to import the base overlay"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 1,
   "metadata": {},
   "outputs": [

This file has been truncated. show original

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MMIO AXI Lite access through an interconnect in IP Subsystem

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