PYNQ: PYTHON PRODUCTIVITY

Need some docs tutorials on pynq drivers

Recently I am tempting to run a self-defined overlay on pynq zcu104.But I have no idea how to write python drivers to control various registers,like AxiLiteS registers shown below.

// Vivado™ HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// ==============================================================
// AXILiteS
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - Channel 0 (ap_done)
// bit 1 - Channel 1 (ap_ready)
// others - reserved
// 0x10 : Data signal of img_V
// bit 31~0 - img_V[31:0] (Read/Write)
// 0x14 : reserved
// 0x18 : Data signal of fm_V
// bit 31~0 - fm_V[31:0] (Read/Write)
// 0x1c : reserved
// 0x20 : Data signal of weight_V
// bit 31~0 - weight_V[31:0] (Read/Write)
// 0x24 : reserved
// 0x28 : Data signal of biasm_V
// bit 31~0 - biasm_V[31:0] (Read/Write)
// 0x2c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)

#define XSKYNET_AXILITES_ADDR_AP_CTRL 0x00
#define XSKYNET_AXILITES_ADDR_GIE 0x04
#define XSKYNET_AXILITES_ADDR_IER 0x08
#define XSKYNET_AXILITES_ADDR_ISR 0x0c
#define XSKYNET_AXILITES_ADDR_IMG_V_DATA 0x10
#define XSKYNET_AXILITES_BITS_IMG_V_DATA 32
#define XSKYNET_AXILITES_ADDR_FM_V_DATA 0x18
#define XSKYNET_AXILITES_BITS_FM_V_DATA 32
#define XSKYNET_AXILITES_ADDR_WEIGHT_V_DATA 0x20
#define XSKYNET_AXILITES_BITS_WEIGHT_V_DATA 32
#define XSKYNET_AXILITES_ADDR_BIASM_V_DATA 0x28
#define XSKYNET_AXILITES_BITS_BIASM_V_DATA 32

Thanks a lot !

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Hi,

The recommended way is to inherit from DefaultIP object and bind to your IP.

https://pynq.readthedocs.io/en/latest/overlay_design_methodology/python_overlay_api.html#creating-ip-drivers

Then you will read and write from the registers

https://pynq.readthedocs.io/en/latest/overlay_design_methodology/overlay_tutorial.html#Creating-a-Driver

As your IP is generated from HLS, PYNQ will populate the .register_map attribute. You can also use this attribute to read/write to your IP.

Mario

Just to add, video example of MMIO here:
https://www.youtube.com/watch?v=zbumITJQ2Z8

Video example of register_map
https://www.youtube.com/watch?v=vK1cEEdKAds&ab_channel=CathalMcCabe

Cathal

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