PYNQ: PYTHON PRODUCTIVITY

Firmware generated with Simulink

I have firmware designed with Simulink, compiled with HDLCoder using Vivado 2020.2. It works with MATLAB calls in their zynq environment.

In MATLAB, here is an example of writing to the “captureCtrl” register:

writePort(hFPGA, “captureCtrl”, false);

where “captureCtrl” is setup like so:

%% AXI4-Lite
addAXI4SlaveInterface(hFPGA, …
“InterfaceID”, “AXI4-Lite”, …
“BaseAddress”, 0xA0000000, …
“AddressRange”, 0x10000);

DUTPort_captureCtrl = hdlcoder.DUTPort(“captureCtrl”, …
“Direction”, “INOUT”, …
“DataType”, “logical”, …
“IsComplex”, false, …
“Dimension”, [1 1], …
“IOInterface”, “AXI4-Lite”, …
“IOInterfaceMapping”, “0x100”);

How would I do this in pynq?

I copied the bit and hwh files and renamed them rdc9.bit and rdc9.hwh and tried this in a notebook:

overlay = Overlay(‘rdc9.bit’)

#the custom IP I want to control is this one:

print(overlay.ip_dict[‘DataCapture_0’])

{‘fullpath’: ‘DataCapture_0’, ‘type’: ‘fnal.gov:ip:DataCapture:1.0’, ‘state’: None, ‘addr_range’: 65536, ‘phys_addr’: 2684354560, ‘mem_id’: ‘AXI4_Lite’, ‘gpio’: {}, ‘interrupts’: {}, ‘parameters’: {‘Component_Name’: ‘system_DataCapture_0_0’, ‘EDK_IPTYPE’: ‘PERIPHERAL’, ‘C_BASEADDR’: ‘0xA0000000’, ‘C_HIGHADDR’: ‘0xA000FFFF’}, ‘registers’: {}, ‘device’: <pynq.pl_server.device.XlnkDevice object at 0x7f84ebb940>, ‘driver’: <class ‘pynq.overlay.DefaultIP’>}

I tried this:

dc0 = overlay.DataCapture_0
print(dc0)
<pynq.overlay.DefaultIP object at 0x7f6d782438>

but this hang and crashes the kernel:

dc0.write(0x100, 0)

1 Like

Usually the hang is from accessing a wrong AXI address. So I would just double check if the base address is correctly configured. Maybe check your block diagram to see if there is any wrong connection?