Axi lite interface read

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1

<custom board, pynq v2.6>
i have a vivado project where smpte uhdsdi tx ss ip has been used. I want to read the register information of it. But unfortunately it is not able to read the register value. Just to mention i am not facing any problem with reading value from other IPs. I am getting following error in command line:

[ 1317.312837] audit: type=1701 audit(1637343679.800:9): auid=4294967295 uid=0 gid=0 ses=4294967295 pid=658 comm="python3" exe="/usr/bin/python3.9" sig=7 res=1
[ 1317.350621] audit: type=1701 audit(1637343679.836:10): auid=4294967295 uid=1000 gid=0 ses=4294967295 pid=657 comm="sudo" exe="/usr/bin/sudo" sig=7 res=1
Bus error

Any suggestion would be really appreciable.

Regards,
Mizan

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2

@mizan

Could you try the template generated from the Vivado and just a simply 32bit register feed forward dummy AXI test?

Forgot to mention, you don’t need to create a driver accordingly. You can direct W/R address via Python. So you got to remember the address map in ZYNQ.

If this is working normal then there must be some protocol logic error inside the IP you had greated.

ENJOY~

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3

Thanks for the reply. I know we don’t need register map. We can write with IP or mmio. In both case it has the same error when i want to access the register space from that ip.

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4

@mizan

Nope you misunderstand my suggestion.

Step 1 write a AXI-Lite register feedforward IP write in store in 1 register and read back the same register.

Step 2 test if this is the problem exist in such dummy IP

The Python code all you need is accessing the address map in the Vivado project. i.e. 0x4000_1000 1kB range

ENJOY~

5

@mizan

For AXI hand written IP adder i.e. I cannot see there is any issue:

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image727×630 17.5 KB

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image694×606 14.2 KB

Double check your IP protocol and tick passing on flops.

ENJOY~

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6

Hi @briansune,
I am not talking about other ip’s. If you go through my first post, you can see I already have stated it. I have some custom IPs in my design as well. Those don’t have any problems, nor do other IPs from Xilinx. Just this particular ip is showing the issue.

Thanks
Mizan

7

@mizan

As you had mentioned, particular IP, aka IP(s) you found had problem might had protocol issues.
How do you know it is not the case?
I do read your initial post issue, so that IP showing such issue is possibly having such issue.

Remember this is PYNQ related forum, so PYNQ Python layer itself had no issue AKA software is stable and sanity must be passed (unless there are very very special cases).
You had double confirmed as well, as your IPs do show no issues.

Or let me make this more clear:

  1. IP from who the hell created might have issue
  2. The connection of AXI-Lite might have misaligned setting or other protocol mismatch
  3. The register control of IP is causing such protocol misalignment (dynamic configured bus)

So unless there are fine detail on these factor and yet off topic to PYNQ forum, it is better to confirm via IP example and familiar yourself with those IP you are using.

ENJOY~

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