Hi Folks, (@stf) I’ve got a (nearly) identical bitstreams built with 2022.1 and 2023.2 and am unable to successfully download the overlay in pynq 3.0.1 on an RFSoC 4x2. When downloading parsing the hwh fails in hwh_frontend.py with a PortNotFound: Could not find physical port s_axi_awid for logical one AWID.
Dropping into the debugger, I’m seeing it is failing to find a match for an s_axi_awid line between two cores in the design (and would also fail on that same bus’ bid line). In both the 22.1 and 23.2 designs these lines are n/c from the RTL core though it looks like they are optimized out at slightly different stages in 22.1 and 23.2. The 23.2 hwh does indeed omit them while the 22.1 does not.
Any help debugging this would be most appreciated.
Hi @baileyji,
If possible, I would suggest you stay with Vivado 2022.1 as it is the version we used to validate PYNQ 3.0.1.
Mario
We are finding that 23.2 has such phenomenally better timing performance than 22.1. I was able to work though these by strategic placement of axi-stream subset converters but then the floodgates opened with other parsing errors. We will keep working on improving 22.1 timing for now.
I have the same problem with one of my designs, Did you find any way to solve this problem in the 2023.2 version?
Thanks
The short answer is no. You can get rid of the portnotfound errors by being pedantic about bus infrastructure but then you will run into other much larger issues. Basically you are own your own if you want 2023 support, which bites as its timing performance is MUCH better.
Thanks for answering,
I also need to use the 2023 version but for now, by the information you provided, I prefer to just skip it 
