Simple BRAM IP Made Through v++, not being detected as a Memory by PYNQ

Support
1

PYNQ v3.0.1, Xilinx Alveo U250: xilinx_u250_gen3x16_xdma_4_1_202210_1

Hello!
I’m having a problem in which I was making a simple BRAM through block design in Vivado 2023.1 and after I finished packaging the IP, I made an xclbin file with it using v++. I am able to use the xclbin file normally and see that the BRAM is being detected properly as a overlay IP, but there are no memories being detected when I do “overlay?” in Jupyter Notebooks. I was wondering if anyone has any kind of example for a simple BRAM using an xclbin file made from using the ip integrator in Vivado/Vitis(v++)

To reproduce the problem:

  1. Create new project in Vivado and make it Vitis extensible

  2. Create New Block Design and match the design below

    bram_bd
    bram_bd772×183 14.4 KB

    a. Make sure to set the BRAM controller to AXI_LITE and to ensure that the
    frequency being used is 300Mhz (its the Alveo U250 default clock speed)
    b. Validate and if asked for auto-addressing say yes

  3. Create a new IP through “Tools → Create and Package New IP”.
    b. In the Compatibility section check the box for “Package for Vitis” and choose
    “user_managed” for the control protocol.
    a. Make sure that in the “Addressing and Memory” tab, that the size of the list in
    there are size 32.

  4. After the IP is packaged, in the tcl terminal type:
    package_xo -force -xo_path /directory/to/store/xo/file -kernel_name krnl_bram -ip_directory /directory/of/packaged/ip/from/step/3 -ctrl_protocol user_managed

  5. Now generate the xclbin file from the xo file generated in step 4
    In your computer’s terminal type:
    $ source /opt/xilinx/xrt/setup.sh
    $ source /tools/Xilinx/Vitis/2023.1/settings64.sh
    $ v++ --platform xilinx_u250_gen3x16_xdma_4_1_202210_1 -t -hw -s -g --link --optimize 1 -o krnl_bram.xclbin /path/to/xo/file/krnl_bram.xo

  6. Now move the xclbin to your Jupyter Notebook directory and use it as the
    overlay. I had the following in my notebook and
    under “Memories” it detects none.

Debugs I’ve done:
I checked with the C++ interface in Vitis and the memory was not detected either.

1 Like
2

I’m working on this with Edwin, and have reproduced this in an independent design.

3

Hi @edro360,

Welcome to the PYNQ community.

What is your goal with this? allocate memory in a BRAM? or just simple AXI4-Lite access?

Mario

4

I was trying to access the BRAM through AXI4-LITE interface since that is how it interacts with the Alveo board’s shell and then allocate/read data passed through the BRAM using PYNQ. Is there some configuration I have to do in order for PYNQ to recognize it as a memory?

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Hi @edro360,

AXI4-Lite interfaces are not mapped as memory. You can still use the MMIO read and write capabilities to access this memory.

Mario

1 Like
6

Hi Mario

How do we know the address of the BRAM? Do we need to add the base address of the PCIE BAR?

Or perhaps another question, how do we make it a mapped memory? AXI4-full?

7

Hi @drichmond,

How do we know the address of the BRAM?

It will show up as an IP, you can access the memory mapped of the IP with MMIO.
Do you see the IP in the ip_dict? If so, you should be able to find all the information there.

Do we need to add the base address of the PCIE BAR?

No, this is done automatically by XRT and PYNQ.

Or perhaps another question, how do we make it a mapped memory? AXI4-full?

I think this is correct, but I haven’t tried it.

8

Huh, Edwin is getting a valid ip_dict, but I am not. Time to debug! Thanks Mario!

1 Like
9

What would cause the addrRemap attribute of the HWH file to be empty in an RTL kernel? This seems to be the root cause.

The .xclbin.info file recognizes the RTL “Function” but there’s no base address assigned.

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Hi @drichmond,

The HWH files is not used for Alveo. All the information should be in the xlcbin.
RTL kernels should have associated metadata to declare the aperture and registers.

Information on how to create this metadata is here

https://docs.xilinx.com/r/en-US/ug1393-vitis-application-acceleration/RTL-Kernel-XML-File

You can check this metadata for a project I have worked on here:

Mario

11

My mistake, I meant the xclbin. Thanks for the correction.

The issue that I seem to be running into is that when I instantiate an IP in IPI, and give it a base address that is not 0x0, the xclbin doesn’t give it a base address in the addrRemap element. Example:

<instance name="kernel_bram_1">            
     <addrRemap base="" range="" port="" />
</instance>

For this xclbin file, the BRAM base address is 0x1000.

This seems to be the root cause of my issue and the difference between Edwin’s successful approach and my unsuccessful approach. Since addrRemap returns None, this line doesn’t evaluate to True:

So even though there’s an IP, and it is in the .xclbin.info files, the PYNQ libraries don’t recognize it. Hence my question “How do we know the address of the BRAM?”.

(Just a theory so far, I’m going to double check all of this again this morning)

12

For this case, you may need to create an xml file and specify the range of the IP and pass that to the package_xo command.

Mario

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Trying that out!

But running into a lot of issues generating the kernel.xml file. For example:

https://support.xilinx.com/s/question/0D54U0000784U80SAE/missing-ports-and-addresses-in-kernelxml?language=en_US

I’ll consider this issue closed. It looks like there is some extra legwork that needs to be done to make PYNQ recognize an IPI design and I’m OK with that.

1 Like