Pynq HDMI test pattern guide issues

Support
1

Hello All,

I am curently having issues following a guide to get an HDMI test pattern showing from my Pynq Z2 Board (https://support.xilinx.com/s/article/932553?language=en_US)

So far I have been able to follow the guide completely start to finish (with a few hiccups - see below) - and Have been successful as to being able to run the Application Project TGP code from Vitis on my Pynq Board over USB, and despite the “TPG started!” message in Putty, my screen remains Sadly black!

Now I know this guide is a bit out of date (Vivado 2018.1 vs me using Vivado 2022.1), but a) another guide said it got it to work (work a vague reference to 'finding the TGP; drivers) and b) it’s the only one I see for generating HDMI graphics (not processing from an input) - Also I am a C developer so I like this over Python.

Here are the hiccups I found with the guide:

  1. 800x600p is not an option for the Video Timing Controller
    -I used 720p instead
  2. When I ‘Validate Design’ I get the error
    " [BD 41-758] The following clock pins are not connected to a valid clock source:
    /v_tc_0/s_axi_aclk"
    copying the example here (PYNQ Test Pattern Generator Hdmi Output - Embedded System & FPGA) and connect it to FCLK_CLK0
  3. From there I make an application project using my .xsa
  4. Because I previously was forced top select ‘720p’ , I changed the ‘XV_tpg_set’ to
    XV_tpg_Set_height(&tpg_inst, 720);
    XV_tpg_Set_width(&tpg_inst, 1280);

Everything else seemed to go smoothy; I left everything else default as I went through.

bd
bd1286×592 59.7 KB

Thanks in advance!!

1 Like
2

Attaching the necessary files since the xilinx links are dead

pynq-z2_v1.0.xdc.zip (7.6 KB)
100018845-65128-xves0023.zip (716.4 KB)

3

@cmhoneycutt343

Simply suggest you check rgb2tmds block.
My memory is lost a bit after year of TMDS encode/decode design.
In general 1080p 148.5MHz is provided.
However does the rgb2dvi block have any AXI update the PLL etc long story short seem it is missing such feature?

Enjoy~

4

@briansune - thanks for the answer - not sure exactly what you mean about checking the rgb2tmds (this is the rgb2dvi IP block right?)

this IP does does appear to have a PLL seeting, and the clock is set to to <80Mhz because my video timing controller is at 720p

image
image1169×896 74.8 KB

1 Like
5

@cmhoneycutt343

PLL is just a general term for clock generation MMCM is what you need for better fractional clock generate.

What I am referring is the control between the firmware when the video timing is generate via the VTC and RGB2DVI only accept the clock from VTC.

You have two choice, RGB2DVI generate the clock to VTC, or VTC generate the clock RGB2DVI.
If the clock is wrongly set, this result in an undecodable TMDS transfer.

image
image795×491 32.4 KB

Can you use a ILA to probe the RGB data line when you run the script or program?
This can easily see is the front-end or the back-end is having issue.

Enjoy~

1 Like
6

@briansune - thanks, I have not yet used the ILA so I will try to get working as I run my program (will this work while I run my .c program from Vitis?

7

@cmhoneycutt343

This post have become a off topic about PYNQ environment nor programming.
It looks like you are having trouble on the FPGA PL design and HDL to firmware flow.
Please ask this at the Xilinx forum as this is not related to PYNQ.

To make this forum better and useful to other PYNQ developer (not just about using the PYNQ board).
The hints are given to you and you need to work out on your side.

Enjoy~

1 Like