PYNQ-Z2 schemeatic about PL I/O

Recently in the use of the board – PYNQ-Z2 , i found that its schematic has the following circuit, do not understand its function ( i have to understand about it), hope to get guidance. Thanks a lot !!!

Hi @ghh,

That is a Voltage divider, the external peripherals use the 3.3 V as power source, so the output analog signal from these peripherals varies between 0 to 3.3 V.
But, the XADC only support an analog input from 0 to 1 V, so that voltage divider does the signal conditioning to meet the XADC requirements.