Could not find IP or hierarchy memory in overlay

I am trying to replicate this repo using the ZCU111 board “PYNQ-CNN-ATTEMPT/FPGA_CNN.ipynb at master · ZhaoqxCN/PYNQ-CNN-ATTEMPT · GitHub” because later I want to change the architecture and run a different dataset, but I am facing some issues with loading the weights on the chip memory.

I have designed my architecture using HLS and then generated IP for my block diagram in Vivado, and I successfully generated an a.bit file. Can someone guide me on how to load the weights into the on-chip memory using an overlay? If someone could give me some suggestions, it would be really helpful to me.
I am using Pynq image v2.7 and a ZCU111 board.


Hi @skalade I was trying to load the basic adder design on the ZCU104 and ZCU111 boards using pynq 2.7 and 2.5 images, but I am still getting this error. Do you have any idea why I am getting these errors? Can you give me some suggestions on how to deal with this?

Thank you.

Hi @Nagendra,

You had asked this question in a different thread. You were suggested to use the overlay.ip_dict to get the IP available in your design. DPU PYNQ on ZCU104 and ZCU111 - #20 by Nagendra

The error is very clear, memory is not an IP in your design. Use overlay.ip_dict.keys() to only show the name of the IP available in your design.


Hi @marioruiz

Thank you for your suggestions. I have solved my issue by adding the IP name to the overlay.