Question about pin assignment and compile error

I am using two 16 TO 1 MUXes to create a switching operation that sequentially applies voltage to 16 electrodes.
Electrodes 1 and 2 → Electrodes 2 and 3 → Electrodes 3 and 4 → … → Electrodes 15 and 16 → Electrodes 16 and 1, and so on.

​For this operation, I create a counter in the fpga and create a signal from 0000 to 1111 to be entered into the select pin of the mux, and the select signal created in this way is pulled from the input/output pin of the pynq z2 board and connected to the two 16 to 1 mux on the breadboard. 1 I want to put it in s0~s3 of mux.

So, if 0000 comes into MUX1, the first LED lights up and this checks the operation of the MUX.

So I created the source code and xdc file in verilog, and below is the code I created.

module Switching(
input wire clk,
input wire reset,
output reg [3:0] select_a,
output reg [3:0] select_b,
output reg sig_a,
output reg sig_b

reg [3:0] counter = 4’b0000;
reg [23:0] timer = 24’b0;

always @(posedge clk or posedge reset) begin
if (reset) begin
counter <= 4’b0000;
timer <= 24’b0;
sig_a <= 0;
sig_b <= 0;
end else begin
if (timer == 24’d5000000) begin
counter <= (counter == 4’b1111) ? 4’b0000 : counter + 1’b1;
timer <= 24’b0;
sig_a <= 1;
sig_b <= 1;
end else begin
timer <= timer + 1’b1;
sig_a <= 0;
sig_b <= 0;

always @(posedge clk or posedge reset) begin
if (reset) begin
select_a <= 4’b0000;
select_b <= 4’b0000;
end else begin
select_a <= counter;
select_b <= (counter == 4’b1111) ? 4’b0000 : counter + 1’b1;


set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {select_a[0]}]
set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS33} [get_ports {select_a[1]}]
set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS33} [get_ports {select_a[2]}]
set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports {select_a[3]}]
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {sig_a}]

set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {select_b[0]}]
set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports {select_b[1]}]
set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {select_b[2]}]
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {select_b[3]}]
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports {sig_b}]

set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS33} [get_ports {clk}]

In this situation, I have two questions.

First, I didn’t know which pins on the board to connect clk and reset to, so I connected them to U7 and P16 as shown in the picture.
Could this be a problem? Since there were no errors in compilation, I am just maintaining this pin status.
If there is a problem with the pin settings of CLK and RESET, which pin should be assigned?

Second, the BITSTREAM creation was completed, but the LED on the breadboard did not light up, so I don’t know what the problem is.
I have connected the breadboard and PYNQ as shown in the picture. The select pin of the MUX is connected through the Arduino shield pin of PYNQ, and voltage is supplied to the MUX through the 5V and GND pins of PYNQ.

Hi @lil_yeongji,

It is likely that you have not connected the clock source to the correct pin. Please, check the user manual to find out the external clock pin or the xdc file. Using vivado on Pynq-Z2 board without PS - #2 by cathalmccabe

Please, note that you need to keep an Ethernet cable connected for this clock to be stable.