Thank you for sharing.
I am getting problems creating custom IPs. I possible, I request can you please answer.
My Verilog code output is 1-bit, and some are less than 32-bit. During synthesis in Vivado, I am getting this error.
- [Synth 8-690] width mismatch in assignment; target has 32 bits, source has 1 bits [“E:/Vivado_CNN/ip_repo/TOP_IP_Image_1.0/hdl/TOP_IP_Image_v1_0_S00_AXI.vhd”:1434]
I am getting this error maybe because “reg_data_out” is 32-bit, and my code output is 1-bit or less than 32-bit.
So, can you please tell me how to reduce the size of the register according to our requirement of can you please tell me any alternative method?