PYNQ version : v3.0.1
Vivado Version : 2020.2
I have gone through the base notebooks and all of them run fine.I tried to rebuild the base overlay by modifying the ip versions in base.tcl ,got the block design but facing issues while bitstream generation.While working on it i got my hands on this design MMIO data format modified the board to RFSoC 4x2 and removed the DAC part.I am feeding signal from a signal generator but the ADC time domain plot is always noisy with or without source.The adc data written is 128 bits and read back is 32 bits .Sampling clk used is 4.1952 GSPS and a decimation of 2 and number of samples is 8 giving an adc frequencyof 307.2 MHz Can someone please help me with where am going wrong .I have attached the block design and jupyter notebook.The time domain plot and fft plots are like this like this with or without source.Is the interpretation of data wrong or the design is the issue?
raw_Adc(1).ipynb (536.8 KB)
hi @Pavithra_B_S
WRT the FFT spectrum you added, is that with or without a signal?
It is without source,even with source the fft plot was quite random .Even for the same frequency fed the tones were different each time
And what data type are you using to represent the data? Also, could you share your RF ADC settings from Vivado?
I have used 4.1952 GSPS with a decimation of 2 and 8 samples.Adc time 224 adc 0 enabled.128 but maxis_tdata connected to din of bram port A with a depth of 256 and port B is 32 bits 1024 depth connected to an Axi bram controller.Am reading through mmio.read as uint32 format it to binary and obtain the 2 samples as 2 16 bit numbers using np.int16 and interleave them into a single array.The data interpretation is available in the jupyter notebook.Also since am using 2 different widths for the ports of bram am using it in standalone mode.Also to check if the number is actually interpreted as we complement I wrote 128 bit constant values and the output seemed fine.
