PYNQ: PYTHON PRODUCTIVITY

Reduce module size

I am working on a project (Ultra96 - PYNQ v2.4) in which I use the lfcW1A2 overlay of the BNN project and the W1A3 overlay of the QNN project.

To avoid constantly switching between overlays I want to combine them into one. For that I rebuilt the Vivado projects of each one following the instructions in the corresponding READMEs. Then I edited one of the IPs so there are no conflicts when using modules with the same name (both use xilinx.org:hls:BlackboxJam so I changed one of them to custom.org:customhls:BlackBox). I created a design with both of them and synthesized it. When trying to generate the bitstream however I realized the result is too big to fit in the Ultra96:

The error is:
[Place 30-640] Place Check : This design requires more Slice LUTs cells than are available in the target device. This design requires 85793 of such cell types but only 70560 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter “drc.disableLUTOverUtilError” to 1 to change this error to warning.

This makes sense as each of the BlackBoxJam modules takes more than 50% of the capacity.

I wanted to ask: is there a way to reduce the size of the modules?

I have some follow up questions but they should probably be in another topic.

Thank you very much for your help!

Hello @mikel,

I think you can change the folding factor of the designs (reuse more hardware). That for sure would impact the hardware performance. But, it will allow you to pack both overlays together.

Mario