Request Help: Real-Time ADC → PL Filter → DAC Pipeline on RFSoC 4x2 Using PYNQ

Support
1

I am currently working with an RFSoC 4x2 board running the PYNQ image, and I need help building a real-time streaming pipeline where:
ADC samples are captured from the RFSoC ADC,
Sent through a low-pass filter implemented in the PL (FPGA),
And the filtered output is streamed back out via the RFSoC DAC.
My goal is that all DSP (filtering) happens in hardware, and the Python notebook only sets up and controls the pipeline — not perform per-sample math in Python. help others learn about PYNQ.

2

Hi @Anees_Rehman1

Welcome to the PYNQ community!

My suggestion would be to look at the open-source examples on the StrathSDR GitHub page for reference designs. There are many designs there that perform similar functionality to what you’re describing.

Additionally, you may find the RFSoC Book useful as well: https://www.rfsocbook.com/

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Thanks