RFSoC 4x2 ADC-DAC Loopback

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Hi

  • Board: Real Digital RFSoC 4x2
  • Tool Version: Vivado / Vitis 2022.1

I am trying to build a direct hardware loopback (a “Digital Repeater” or delay line) on the RFSoC 4x2. Most tutorials and examples online focus on generating a signal on the DAC and reading it back on the ADC. My goal is the exact opposite: I want to feed a physical Signal Generator into the ADC, capture/route that data through the PL, and instantly broadcast it out of the DAC to an oscilloscope.

I initially started with the Xilinx MTS (Multi-Tile Synchronization) example project to avoid configuring the clock and starting from scratch ( GitHub - Xilinx/RFSoC-MTS: A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS). · GitHub ) , but I am running into severe AXI-Stream pipeline blockages when trying to route the data.

For the PL I have tried connecting the ADC’s m_axis to the DAC’s s_axisdirectly and then using standard AXI4-Stream Data FIFOs but it didn’t work. I created a 10Mhz signal at -10dB for the input and in the output there’s nothing.

When i run:

adc_status = rf.adc_tiles[2].blocks[0].BlockStatus
print("\n--- ADC Hardware Status ---")

# Safely print everything inside the status dictionary
for key, value in adc_status.items():
    print(f"{key}: {value}")

my output is:

--- ADC Hardware Status ---
SamplingFreq: 4.0
AnalogDataPathStatus: 1
DigitalDataPathStatus: 17
DataPathClocksStatus: 1
IsFIFOFlagsEnabledIsFIFOFlagsEnabled: 3
IsFIFOFlagsAsserted: 3

And i understand that IsFIFOFlagsEnabled = 3 means there’s a crashout in the FIFO, but i dont really know how to debug this, because i haven’t changed the clock configuration from the MTS project.

If anyone can help me with an idea or if this project has been done before with this exact board will be really helpful for me if you share it.