Hi,
I’m using an RFSoC4x2 with a custom overlay derived from the RFSoC-PYNQ base design.
I can successfully send data through the TX DMA and receive data through the ADC DMA. The RFDC tiles are enabled and locked, DMA transfers complete correctly, and DAC_A is connected directly to ADC_A with an SMA loopback.
However, when I transmit a known waveform (custom IQ samples), the received signal appears mostly as low-level noise/DC rather than the transmitted waveform.
My main question is: What is the exact AXI-Stream sample format expected by the RFDC DAC input on RFSoC4x2?
For example, if a 256-bit AXI beat carries 8 complex samples, should the samples be packed as:
I0,Q0,I1,Q1,I2,Q2,I3,Q3,I4,Q4,I5,Q5,I6,Q6,I7,Q7
with each I/Q value represented as a signed 16-bit integer, or is a different ordering expected?
The RFDC configuration currently uses:
DAC: I/Q mode, interpolation ×2, 8 samples per AXI cycle
ADC: I/Q mode, decimation ×2, 8 samples per AXI cycle
Fine mixers enabled with NCO frequency set to 0 Hz on both TX and RX
At this point I suspect one of the following:
Incorrect I/Q sample packing.
Incorrect AXI lane ordering.
RFDC TX/RX configuration mismatch.
Are there any RFSoC4x2 examples showing the exact DMA buffer format expected by the RFDC DAC input?
Thanks.
I’ve never run I/Q mode but have run the 4x2 with straight through mode
at full speed (4 GHz sampling rate) derived from the MTS example and it
works feeding it sequential 16 bit samples. I do see low-level noise
on the signals from the ADCs.
Are you sure that you have the cable between the DAC and ADC connected
to the correct channels? In particular, I’ve found that ADC B is ADC
2 internally. You might try the other ADC channels and/or use some
external instrument to observe the DAC output.
Another thought, the NCO is digital and might start with an output value
of zero. And at 0 Hz this will never change. So each sample is being
multiplied by 0?
Other than that, there are the variable output power and attenuator
settings, but I don’t know if they go to zero.
Hi, figured I’d reply in case you also had the same issue as me. As labelled on the RFSoC 4x2 board, DAC A corresponds to tile 230, DAC 0 in the IP block and ADC A on the board is tile 226, ADC 1 specifically. I observed just noise for some time with a working system driving the wrong one.
Thanks for the suggestions. I believe those issues are now resolved.
I verified the physical TX/RX path using a continuous 8 MHz complex tone generated in software and sent through the TX DMA. The received signal is stable across repeated captures, the received power is consistent, and cross-correlation between captures gives a peak lag of 0 samples. This suggests that the DAC, ADC, DMA path, mixer configuration, and channel mapping are working correctly.
My current RFDC configuration is different from the one in my original post. I am currently running:
- DAC sampling rate: 1.024 GSPS
- ADC sampling rate: 1.024 GSPS
- DAC interpolation: 8
- ADC decimation: 8
- Effective AXI/Python sample rate: 128 MSPS
- DAC mixer mode: I/Q → Real
- ADC mixer mode: Real → I/Q
I can successfully transmit and receive both an 8 MHz tone and Zadoff-Chu waveforms.
The remaining issue is not signal detection but deterministic synchronization. When transmitting finite-length Zadoff-Chu frames, the correlation peak position changes significantly between runs even though the normalized correlation peak remains fairly constant. This suggests that the waveform is being received correctly, but the relative TX/RX start timing is not deterministic.
At this point I suspect the problem is the synchronization between the TX DMA start and the RX packet generator trigger rather than the RF path itself.
Has anyone implemented deterministic synchronization between TX and RX on the RFSoC 4x2 when using DMA-based waveform transmission? Did you use a shared PL trigger, GPIO pulse, TLAST-based control, or another mechanism?