RFSOC ADC does not seem to come out of reset

I am using PYNQ with ZCU111 RFSOC board. I have probed the design hardware using ILA’s and I can see that the RF data converter has ADC and DAC clock out active, indicating it has all the clocks it needs.
None of the reset pins are being asserted and the adc_status[3:0] bus indicates 0xF . However when I monitor the output of the master axis busses driving the ADC digital output, I see there is no activity. The Axis interface tready and tvalid flags are also asserted.

The lack of activity from ADC must surely mean it is being held off somehow. Doe sanyone have a sample PYNQ Python file that wakes up the ADC? attached is one I have tried to use.

Many thanks,

Simon (4.3 KB)

Hi @SimonHildebrand

I don’t have experience with RFSoC on Pynq, but on my latest design using the RF DC block, it was important to hold its main reset asserted until the external PLL had locked and all its clocks in working order before deasserting reset.
In your code, that may mean moving the LMX clock initialization to happen before the usp_rf_data_converter is instantiated.


Hi Pat,

Many thanks for your reply. I will try and do as you suggest.
I have started a new thread to address controlling the reset.