ZCU111 which PYNQ function is used to toggle PL reset

Support
1

Hi,

I have a simple ZCU111 project which has four ADC and four DAC channels.
Unfortunately I cannot get the ADC to output any data, so I checked the all the clocks, PLLs etc and all are running. I beleive the ADC won’t start up until it is reset.

Then I looked at the pl_resetn0 coming out of the ZYNQ processor, I have this drive an external pin, so I can monitor it.

Unfortunately I can never assert reset .
I can re program the PLLs ADC & DAC tiles etc, but I do not know how to drive this reset pin using PYNQ.

Regards Simon

reset_pl
reset_pl1233×805 97.3 KB

2

Have you checked this page:
https://www.xilinx.com/support/answers/68962.html

3

@SimonHildebrand

Here’s an idea how to assert the RF IP reset (s_axi_aresetn) without changing the pl_resetn0 state. “AND” the pl_resetn0 signal with a signal you control from e.g. MMIO into the RF IP, and after your clock configuration is completed, you would pulse this MMIO reset. Ideally, no software would access the RF IP while its reset is asserted, or bad things can happen™.

Thanks,
-Pat

4

Hi,

Thanks for directing me to this. Unfortunately when I try this, I find that the GPIO[95] is NOT mapped to PL resetn0. It seems to remain available.

Thanks for the link to AR#68962