Hi I have written IP in verilog, I want to be send a vector of input data, where each item in the data is a 32 bit integer. My module requires all of them - each element in the vector is dependant on others in the same vector basically. For instance my module’s inputs are:
input logic [31:0] i_input_1
input logic [31:0] i_input_2
etc
input logic i_valid.
I then output 20 32 bit numbers on separate output ports.
I want to use DMA to send an array of inputs and receive an array of outputs. How do I make my module compatible for this so that I can just input my vector of data, and then read the output vector accordingly.
Tutorial: PYNQ DMA (Part 1: Hardware design) - I have read this and the part after, but it doesn’t tell me much about how to modify my own verilog code.