The output image of HDMI in ZCU104 was divided

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1

Hello, I’m tring to add my design in the tutorial design. But the output image was cut. The following is the step that I did.

  1. rebuild the base.tcl
  2. I connect my design to Zynq UltraScale+ MPSoC using DMA, the picture will show the pins I connect
  3. Double click the cpu and find PS-PL Configuration then choose the AXI HPM0 FPD, AXI HPC0 FPD and AXI HPC1 FPD
  4. Then connect the pins. The detail can saws in the picture.

Then I put the bitstream on the board, and start it. But The output image was wrong. This code was the same then I doing this in PYNQ Z2.
Is some pins was connected wrong? or Is some setup was wrong?base.pdf (358.5 KB)

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3

It is difficult to determine what the problem might be as you haven’t really provided much info.
Which version of PYNQ?
Why did you rebuild the base design?
Did you make any changes?
What Python code are you using?
What is the original image, what should the output look like?
What output resolution are you using?
What have you tried to debug this?
etc.

Cathal