Tlast signal and Vitis HLS

Support
1

Hello,
I am trying to implement the stereolbm algorithm from the Vitis Vision Library. I am working with an Ultra96v2 (PYNQ version 2.5), Vitis HLS 2023.2, and Vivado 2023.2.
I followed a tutorial that allowed me to modify the source file to implement HLS stream and DMA. When I try to transfer the files, I cannot get past the wait() phase. While reading around, I found that in the interface created for stream_inL, stream_inR, and stream_out, there are no TLAST signals. I understand that this is a problem related to the use of Vitis HLS, but I cannot solve it. I am sharing my HLS source and also the design in Vivado. Thank you very much in advance.

image
image1247×446 62 KB

xf_stereolbm_accel.cpp (9.2 KB)

xf_stereolbm_config.h (1.7 KB)
.2 KB)

2

Hi @T_A,

Welcome to the PYNQ community.

What tutorial did you follow? The Vitis/Vivado that are you using is much newer that the one that was used to verify PYNQ 2.5.

Mario

3

Hi, thank you for your reply. This is the tutorial that I followed: https://community.element14.com/technologies/fpga-group/b/blog/posts/zynq-stereo-camera-platform---part2-stereolbm-with-vitis-vision-libraries?focus=true

4

Hi @T_A,

For that example, they are using Vivado 2020.1 StereoIPcores_MPSOC/stereolbm.tcl at main · Q-point/StereoIPcores_MPSOC · GitHub

The constructs that you’re using the HLS code are will not work in the Vitis HLS 2023.2

Mario

5

Thank you for your reply. Can you tell me how to modify it to make it work? In general, how to change the functions of Vitis Vision Library to have the axi stream interface?

6

You can see how I did it here PYNQ_Composable_Pipeline/src/erode/erode.cpp at v1.1.0-dev · Xilinx/PYNQ_Composable_Pipeline · GitHub

7

Thank you. I edited the HLS file and am now able to see Tlast. In the notebook, however, I get stuck in wait().I’ve read that using wait() and PYNQ 2.5 always results in my error. The solution seems to be to move to PYNQ 2.4 Any help? Thank you

8

I wrote an extensive piece on debugging DMA issues, this is most likely because the video signaling are not working as expected.

9

I’m sorry, I’ve already read this post several times without finding the answer to my problem. Sharing my notebook, hope it helps.
stereoLBM_PYNQ_Test.ipynb (231.2 KB)

10

In which wait is your code hanging?

You should do first output_dma.recvchannel.transfer(out_buffer) then output_dma.recvchannel.wait()

You may also want to check that the register mapping is correct. Instead of using the offset, I suggest you use the register_map

Mario

11

Hi, I really appreciate your help. Unfortunately, I have problems with each of the three wait()s in my code. Also, I checked the PYNQ version and it’s not 2.5, but 2.4. Thanks so much again.

12

I just noticed that if I try to use register_map with the bitdepth ip it gives me this error: AttributeError: ‘Registerwidth’ object has no attribute ‘_buffer’. Can this information help?

13

Can you please share the notebook you are using?

14

stereoLBM_PYNQ_Test.ipynb (231.2 KB)

15

Hi @T_A,

I think you should revisit how the vision IP expect tlast and tuser. If you want to use the vision library as it is, you should use a VDMA IP. Otherwise, you may want to double check how your IP expect those signals.

Mario

16

Hi, thanks for your reply.
I’m not using the Vitis Vision library as it is, I modified it to create the axi stream interface and now I’m able to synthesize it correctly. Is there a possibility that PYNQ 2.4 version is not compatible? Could upgrading to a new version solve my wait() problem?

17

Is there a possibility that PYNQ 2.4 version is not compatible?

Unlikely, but if you’re using a Vivado version that was not tested for this version is possible.

I modified it to create the axi stream interface and now I’m able to synthesize it correctly.

How are you handling TLAST in your IP? Is it asserted at the end of the image or at the end of line?

18

Thank you for your reply and for your dedication. This is the way I use to handle the communication between the IP core (outgoing) and the DMA:

template <int TYPE, int HEIGHT, int WIDTH, int NPPC>
int xfMat2AXIstreamwide(xf::cv::Mat<TYPE, ROWS, COLS, NPPC>& img, stream_out& 
AXI_video_strm) {

ap_axiu<32,1,1,1> pixelpacket;
int res = 0;

int rows = img.rows;
int cols = img.cols;
int idx = 0;

assert(img.rows <= ROWS);
assert(img.cols <= COLS);

bool sof = true; // Indicates start of frame

loop_row_mat2axi: for (int i = 0; i < rows; i++) {
	loop_col_mat2axi: for (int j = 0; j < cols; j++) {
		// clang-format off
		#pragma HLS loop_flatten off
		#pragma HLS pipeline II=1
		// clang-format on
		ap_uint<1> tmp = 0;
			if ((i==rows-1) && (j== cols-1)) {
				tmp = 1;
			}

			pixelpacket.last = tmp;
			pixelpacket.data = img.read(idx++);

			AXI_video_strm << pixelpacket;

		}
	}

return res;

}
I send 320x240 images where each pixel is 16 bit. stream_out is defined as:

typedef hls::stream<ap_axiu<32,1,1,1>> stream_out;
19

I suggest check the size of the transfers, you allocate buffers using uint8 (grayscale) but then the pixels in your IP use 32-bit which assumes RGBA.

20

sorry, i sent you the wrong code. In the example i’m using i defined 16 bits in output (the stereolbm ip produces a 16 bit disparity map). i also removed the convertbitdepth ip and changed the allocated buffer in the notebook, now it’s 16 bits. i don’t think it’s a size issue, however i still can’t get past the wait() execution. Are there any examples using the Vitis Vision library and axi stream?