TLAST signal not synthesized!

[Yousef_Alnaser]

Hello all,

I’m using an axis interface for data in and out (eventually using DMA) but with floating point type. So i need to set the TLAST signal manually, as a million tutorials suggested. But in my case, it doesn’t get synthesized for some reason.
Here is my code:

void fit(hls::stream<axis_t> &in, hls::stream<axis_t> &out, float lambda, float gamma) {

#pragma HLS INTERFACE axis port=in
#pragma HLS INTERFACE axis port=out
#pragma HLS INTERFACE s_axilite port=lambda
#pragma HLS INTERFACE s_axilite port=gamma
#pragma HLS INTERFACE s_axilite port=return

...

and the data type is defined here:

typedef struct {
	float 		data;
	ap_uint<1>	last; // tried it with bool and ap_int as well!
} axis_t;

//another variation
//struct axis_t {
//	float 		data;
//	ap_uint<1>	last; // tried it with bool and ap_int as well!
//};

the synthesis report shows this with no TLAST signal:

Why the TLAST signal is not getting synthesized, though in all of the tutorials online, it deos?

[marioruiz]

Hi @Yousef_Alnaser,

In Vitis HLS, to use AXI4-Stream with sideband channels, you cannot use a custom structure. You need to use one of the pre-defined templates, such as ap_axis<32,0,0,0>

I recommend you read this tutorial

Tutorial: using a HLS stream IP with DMA (Part 1: HLS design)

Tutorial: using a HLS stream IP with DMA tutorial (Part 1: HLS design) In a previous tutorial I showed how to use the AXI DMA to stream data between memory to AXI stream interfaces. The DMA tutorial used an AXI stream FIFO to do a loopback test to show how to use the DMA. This tutorial will show how to create and add a HLS IP with an AXI input stream, and AXI output stream. This tutorial will be split into two parts. This part 1 shows how to build the HLS IP, part 2 shows how to build the Vivad…

Mario

[Yousef_Alnaser]

Hello @marioruiz,

Well, I was looking through these links: from stackoverflow and from this website, and I have many more which all say it could happen.

Maybe I’m missing something or maybe it is changed? using ap_axis, I have to convert to/from float each time i write/read, right?

[mizan]

@Yousef_Alnaser

I was looking through these links: from stackoverflow and from this website, and I have many more which all say it could happen.

They and you are right about it if you are using Vivado HLS, but in Vitis HLS if you are not using predefined template as Mario stated, the sidechannels mostly compressed and if not compressed they gave some weird pin outputs. So, if you want to use Vitis HLS, use predefined templates, otherwise open vivado_hls from command prompt, it will work there.

[Yousef_Alnaser]

hello @mizan,
Sadly, I’m using Vitis HLS 2021.1 (and 2021.2). I’ll try to do the solution twice, once on Vitis HLS as Mario suggested, and I would like to try it on Vivado HLS! Thank you again.

One thing though, As far as I know vivado_hls is retired, and replaced by vitis_hls, do I need to install an older version? or can i launch it from the already intalled xilinx unified platform?

[cathalmccabe]

Why do you want to try Vivado HLS? As others mentioned, there are differences between how you do this with Vivado HLS and VItis HLS.
As Vitis HLS is the new version I would recommend you learn how to do it with Vitis HLS and ignore Vivado HLS.

Cathal

[marioruiz]

Hi @Yousef_Alnaser,

You are looking at posts that are using Vivado HLS, so what it is mentioned there does not apply, as @mizan mentioned as well.

I do not recommend to use Vivado HLS either.

For 2021.2 look at this example, Vitis-HLS-Introductory-Examples/Interface/Streaming/using_axi_stream_with_struct at master · Xilinx/Vitis-HLS-Introductory-Examples · GitHub

You can define the type of the data as hls::axis<float, 0, 0, 0>

Mario

[Yousef_Alnaser]

Will do, thanks

[Yousef_Alnaser]

I didn’t know this existed, tbh. Newbie here. But thank you very much! this already solved my problem.

[rashedkoutayni]

@cathalmccabe @marioruiz @mizan
I am using Vitis HLS 2020.1 and I use the pre-defined ap_axiu<32,2,5,6> for input and output streams. I also use the appropriate interface pragma to indicate that the input and output streams are axis ports:

void TOP_LEVEL_FUNC(hls::stream<ap_axiu<32,2,5,6>> &Input1_stream, hls::stream<ap_axiu<32,2,5,6>> &Output1_stream){
#pragma HLS INTERFACE s_axilite port=return bundle=CTRL_BUS
#pragma HLS INTERFACE axis port=Input1_stream
#pragma HLS INTERFACE axis port=Output1_stream

However, I still get TDATA=96 bits, TVALID=1 bit and TREADY=1 bit after C synthesis, whereas I don’t get any TLAST signal!
I checked the synthesis report and the generated VHDL code and haven’t found any TLAST signal.

    ...
    Input1_stream_V_TDATA : IN STD_LOGIC_VECTOR (95 downto 0);
    Output1_stream_V_TDATA : OUT STD_LOGIC_VECTOR (95 downto 0);
    Input1_stream_V_TVALID : IN STD_LOGIC;
    Input1_stream_V_TREADY : OUT STD_LOGIC;
    Output1_stream_V_TVALID : OUT STD_LOGIC;
    Output1_stream_V_TREADY : IN STD_LOGIC );

I followed what is recommended in this post, still I am not able to get TLAST synthesized (although this was working when I was using Vivado HLS).

Any suggestions please?
Thanks !

[marioruiz]

With that version of the tool, please use Vivado HLS.

Mario