You should change the INTERFACE to AXI STREAM (axis ) or AXI MASTER (M_AXI).
It looks like you changed it to M_AXI (AXI MASTER) in the last screenshot.
If you use AXI masters you can follow this post:
https://discuss.pynq.io/t/tutorial-axi-master-interfaces-with-hls-ip/4032/4
Cathal
PS
If you use AXI STREAM you need a DMA.
https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133/28
https://discuss.pynq.io/t/tutorial-using-a-hls-stream-ip-with-dma-part-1-hls-design/3344/2