Two bitstreams and the location of both are overlapping

Hello there,

If I use vivado and set in the floorplan pblocks location for each different design.

It suppose that pynq enviroment will give me an error in runtime if I try to load two bitstreams and the location of both are overlapping. Right?

Adding this post to a new topic. Please open a new topic for separate issues.

The FPGA is a physical device. You either configure it all at once with a single bitstream, or part of the device with a partial bitstream.

If you have two (full) bitstreams, when you download one, it will overwrite whatever was there previously.

Partial bitstreams need to be planned carefully. You would have a distinct PR region, and only overwrite this region to replace the previous function. You would not have overlapping block as this would not work.


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I expressed wrong, was referring about partial reconfiguration.
It’s all clear now, thank you very much Cathal!