Pr_download is failed (partial reconfiguration)

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1

First, I made a following design and generated bitstream.

image

Next, I wrote “top.bit” as a full bitstream on the board and downloaded it. The full design worked correctly. (I use pynq version2.5.)

overlay=Overlay(“top.bit”)
overlay.download(“top.bit”)

I downloaded a partial bitstream on the reconfigurable partition, but I received some errors.
Error messages are as follows(“Could not find IP or hierarchy reconfiguable_partition_A in overlay”). I tried many times, changing the partial region name or file name, but situation is not changed.

image

I can write the partial bitstream via JTAG, so I think the settings of partial region are correct.
I read the documentation about partial reconfiguration, but the information is about v2.4 and cannot found the information of v2.5.(Partial Reconfiguration — Python productivity for Zynq (Pynq))

How should I do in order that the design recognizes the existence of partial region?

2

Is you reconfiguable_partition_A in the main block design? You should not put that hierarchy under any other hierarchies. You must have overlay.reconfiguable_partition_A available, otherwise it will fail.

3

Thank you for reply.

I did not put reconfiguable_partition_A in the main block design.

I tried to remake design and put reconfigurable partition in the main block design, but I received the error message, “IP type module cannot be made into partition definition. Create a RTL wrapper on the IP and then create the Reconfig Module.” I created new block design including partial reconfiguration module and executed “Create HDL wrapper”. However, the new block design is not able to be added to main block design.

My design is here. “system_wrapper” is the main block design, and “design_1_wrapper” is the partial reconfiguration block design. What should I do to add design_1_wrapper to system wrapper? Or am I mistaken?
image

4

Have you checked Partial Reconfiguration on Vivado 2018.3 with PYNQ - YouTube

5

Thank you for letting me know.
It has been successfully resolved.

6

How did you resolved it? I tried and could get my PR into the block design and it builds the PR’s bit-files. But I cannot program the partial bit-file with PYNQ it says hierarchy not found. When listing it finds no hierarchy.

7

Does the module in PR region have memory mapped interface, such as AXI?
As far as I know, pr_download can recognize only memory mapped interface.

8

I have a wrapper (called “filter” which is my PR) around the FIR-compiler which has Axi-stream interface, which is connected to a DMA (not PR). I can see the DMA but not the “filter”-block, in PYNQ.

9

Hi @gus,

PYNQ will only show IP that have an AXI4-Lite interface and map them to the ip_dict

Currently, pure AXI4-Stream kernels are not visible from pynq.

Mario

10

Hi @marioruiz ,

Thanks for the reply.
So could I put the DMA in a hierarchy with the FIR-compiler to make it work as a Partial reconfig or some other a block with AXI4-Lite interface?

11

Yes, that should work,

Mario

12

Hi again,

I did put the DMA inside the filter-block. However I can not figure out how to connect to the DMA. Neither can I set the partial region. Sorry for not understanding this. Attach my block design and the output from “overlay?”:

Design_pr
Design_pr1424×657 55.6 KB
![filter_block|690x295]
Type: Overlay
String form: <pynq.overlay.Overlay object at 0xafb7b1b0>
File: /usr/local/lib/python3.6/dist-packages/pynq/overlay.py
Docstring:
Default documentation for overlay /root/pynq-z2/design_1/design_1.bit. The following
attributes are available on this overlay:

IP Blocks

filter/S_AXI_LITE : pynq.overlay.DefaultIP
processing_system7_0 : pynq.overlay.DefaultIP

Hierarchies

filter : pynq.overlay.DefaultHierarchy

Interrupts

None

GPIO Outputs

None

Memories

processing_system7_0 : Memory

13

Hi @gus,

You are asking for help with an advanced Vivado feature. You may be better posting on the Xilinx forum:

https://forums.xilinx.com/

Or follow the DFX documentation

Mario