roka
August 28, 2019, 7:21am
1
Hello
I am using the Ultra96 board with Pynq:
(PYNQ Linux, based on Ubuntu 18.04 (GNU/Linux 4.14.0-xilinx-v2018.3 aarch64))
I just have a basic issue with the assignment of the PL HD_GPIOs.
First I need a hint where to find the default base.bit file. Then I need to know how to adapt it to assign the mentioned GPIOs 0-14 to be able to control them over Python.
Have someone an example bit file?
Thanks in advance.
Roger
1 Like
Hi Roger,
You can find PYNQ docs related to the Ultra96 here: Welcome to Ultra96-PYNQ’s documentation! — Ultra96-PYNQ v2.6 documentation
If you want to change pin assignments, the project files for the base overlay are here:
(This can be found from the previous link)
Cathal
1 Like
roka
August 28, 2019, 10:57am
3
Thank you for your feedback.
I checked the pages already, but I still need some add support.
for example:
Can I adapt the .bit files on the pynq directly without vivado? (dont understand the doc in details)
If yes, where I have to add the GPIO Configuration?
Regards
Roger
1 Like
What do you want to do with the board?
You need to modify the design in Vivado if you want to change the design, but you may not need to do this.
Cathal
1 Like
roka
August 28, 2019, 12:55pm
5
I will have a simple Python programm running on the PS (pynq) part, which needs to control 14 GPIOs (as output (0/1)) which are on the PL side (HD_gpio_0 - 14).
1 Like
If you want to build your own design, I suggest you install Vivado, and follow the instructions to rebuild the existing base design.
You could try follow parts of this tutorial to add an AXI GPIO controller to connect to the pins you need:
Creating a new hardware design for PYNQ
The previous tutorial showed how to rebuild the reference base design for the PYNQ-Z1/PYNQ-Z2 boards. This tutorial will show you how to create a new Vivado hardware design for PYNQ. This tutorial is based on the v2.4 PYNQ image and will use Vivado 2018.2. The PYNQ-Z2 board was used to test this design.
If you are using the PYNQ-Z1 or PYNQ-Z2, first make sure the board files have been installed. Download the PYNQ-Z1 board files or the PYNQ-Z2 board files ,…
(You only need 1 AXI GPIO controller, and you don’t need the BRAM controller).
Cathal
1 Like
roka
August 29, 2019, 1:06pm
7
Thank you. Now the bit tcl and hwh files are done and in the pynq dir.
Now I have to load the Overlay (design_1.bit) file over the /pynq/overlay.py?
1 Like
Yes, just add the path to your .bit when instantiating the overlay
overlay = Overlay(“./path/to/my.bit”)
https://pynq.readthedocs.io/en/v2.4/pynq_overlays/loading_an_overlay.html
Cathal
1 Like
roka
August 30, 2019, 9:38am
9
Hello
So,now it worked so far.
But I only see 1 axi_gpio:
instead of 14.with the “overlay.ip_dict.keys()”
How can I see all listed?
Wih kind regards
Roger
You should only have one controller, connected to 14 pins.
If you use the PYNQ AXI GPIO class, you could write 0x3fff, to set all the pins to 1.
Some other material/examples here of AXI GPIO
{
"cells": [
{
"cell_type": "markdown",
"metadata": {},
"source": [
"# Using AXI GPIO with PYNQ\n",
"\n",
"## Goal\n",
"\n",
"The aim of this notebook is to show how to use AXI GPIO from PYNQ. \n",
"\n",
"Multiple AXI GPIO controllers can be implemented in the programmable logic and used to control internal or external GPIO signals.\n",
"\n",
"## Hardware design\n",
"\n",
"This example uses a bitstream that connects three AXI GPIO controllers to the LEDs, buttons, and switches and can be used with the PYNQ-Z1 or PYNQ-Z2 board. (Each AXI GPIO controller has 2 channels, so multiple peripherals could be controlled from one AXI GPIO IP, but for simplicity and demonstration purposes, separate AXI GPIO controllers are used. \n",
"\n",
"![AXI GPIO Design](./images/axi_gpio_design.png \"AXI GPIO Design\")"
]
This file has been truncated. show original
Cathal
roka
August 30, 2019, 12:55pm
11
It looks good. Have to adjust some Pins, will give you a feedback next week.
Thanks a lot so far, was a great help!
Regards
Roger