Unable to create setup with 2 ADCs enabled in 2 tiles in Pynq RFSoC4x2

Support
1

I am unable to test a setup where 4 ADCs are enabled (2 ADCs each in Tile 224 and Tile 226). The POR and INIT LED on board goes red when I use the vivado tcl shell to give read and write commands. Could you please give a solution to resolve this issue?

I would also like to get a Vivado 2022.2 example design where 4 ADCs are enabled for Pynq RFSoC 4x2

2

Hi @Shreela

I would suggest looking at the various RFSoC designs from StrathSDR. They might have a design you can work from.

3

Hi,

I have got the example setup for testing all the 4 ADC’s on Pynq4x2 Board. But while generating the bitstream I am getting an error “[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
base_i/CMAC/cmac/inst/i_base_cmac_0_top ()
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.”

I opened the CMAC IP core. It shows on the bottom left corner that “Design_Linking IP License is Available”

Please provide a solution to rectify the same

4

Hi @Shreela

This forum post might be related to your issue: AMD Customer Community

5

Hi @Shreela ,

It seems you are missing license for CMAC IP, for the QSPF port. You need to get that licence or remove it from the design to continue.

Best