Using migen and chisel on pynq boards

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Hi,

The pynq package allows us to interact with the PS and PL quite well.

Just out of curiosity, I wanted to know if we could write the verilog codes for the PL in the new languages like migen and chisel on pynq supported boards.

Is it possible? Is it a good idea to pursue?

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Hardware design is orthogonal to PYNQ. You can choose to build the PL design any way you want. Ultimately these languages generate RTL. As long as you import the generated IP into an IPI block diagram in Vivado, you can use the design with PYNQ.
There is more detail to consider, but at a high level, yes, it should be possible.
Is it a good idea? I don’t know :wink:

Cathal

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Yes I think it is a good idea to proceed (use newer language to generate RTL and import the generated IP into IPI bd).

Both these workflows(RTL generation and Vivado bitstream gen workflow) are independent so I guess there would not be any problem to make it work.

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Hello adbyoyo,

CHISEL -< " Constructing Hardware In a Scala Embedded Language" is not HLS. It is a advance replacement to Verilog poor parametric structure and syntax reduction via Scala.

Before Chisel arrive SpinalHDL is already well develop and all syntax are welly documented.

Both of them just replace Verilog or VHDL to a better environment.
You may find out even both of these language are trouble with FSM case as no matter what language you are in HDL field FSM is just the same tedious structure.
However, when come to pipeline structure it is a completely new world on CHISEL.
Not even HLS on C/C++ can be that beautiful as CHISEL.

Enjoy~

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